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Hi, I want to generate a symbol from a simple VHDL file, but symbolator don't recognize the file or something else.
reset_generator.vhdl.txt
I use symbolator 1.0.2 hdlpasrse 1.0.4
The text was updated successfully, but these errors were encountered:
Hi, it may work if you remove the header comments. Still a bug, but it works on my own VHDL files.
Great work @kevinpt , btw! 👍
Sorry, something went wrong.
Same for my files, no output is generated and programs ends with no error.
Merge pull request kevinpt#4 from daniellimws/antmicro-improvements
97f24de
Merge improvements from antmicro's fork
No branches or pull requests
Hi,
I want to generate a symbol from a simple VHDL file, but symbolator don't recognize the file or something else.
reset_generator.vhdl.txt
I use
symbolator 1.0.2
hdlpasrse 1.0.4
The text was updated successfully, but these errors were encountered: