fcvtmod.w.d not hitting OF or NX flag bins

[davidharrishmc]

fcvtmod.w.d is not setting the NX coverage bins.

Converting the most positive number sets the invalid flag instead of the overflow flag.

Converting 1.5 does set the inexact flag in Sail but it is not showing up in the bin.

wsim rv64gc tests/rv64/ZfaD/WALLY-COV-fcvtmod.w.d.elf --lockstepverbose > log
# Info 1464: 'refRoot/cpu', 0x00000000800016dc(rvtest_entry_point+16dc): Machine 00013d87 fld     f27,0(x2)
# Info   MEMX 0x800016dc 0x800016dc 2 3d87
# Info   MEMX 0x800016de 0x800016de 2 0001
# Info   MEMR 0x80004000 0x80004000 8 3ff8000000000000
# Info   f27 ffabeda7d0cc03b3 -> 3ff8000000000000
# Info 1465: 'refRoot/cpu', 0x00000000800016e0(rvtest_entry_point+16e0): Machine c28d99d3 fcvtmod.w.d x19,f27,rtz
# Info   MEMX 0x800016e0 0x800016e0 2 99d3
# Info   MEMX 0x800016e2 0x800016e2 2 c28d
# Info   x19 973c57e755a1f1ef -> 0000000000000001
# Info   fflags 0000000000000000 -> 0000000000000001 [NV:0 DZ:0 OF:0 UF:0 NX:0->1]
# Info   fcsr 0000000000000000 -> 0000000000000001 [NV:0 DZ:0 OF:0 UF:0 NX:0->1 FRM:0(RNE)]

The coverpoint looks ok.

covergroup ZfaD_fcvtmod_w_d_cg with function sample(ins_zfad_t ins);
...
    cp_csr_fflags_vn : coverpoint get_csr_val(ins.hart, ins.issue, `SAMPLE_BEFORE, "fcsr", "fflags") iff (ins.trap == 0 )  {
        //Value of FCSR.fflags
        wildcard bins NV  = (5'b0???? => 5'b1????);
        wildcard bins NX  = (5'b????0 => 5'b????1);
    }

But the NX flag bins is not hit.

    Coverpoint cp_csr_fflags_vn                        50.00%        100          -    Uncovered            
        covered/total bins:                                 1          2          -                      
        missing/total bins:                                 1          2          -                      
        % Hit:                                         50.00%        100          -                      
        bin NV                                              1          1          -    Covered              
        bin NX                                              0          1          -    ZERO