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[ImportVerilog] Add foreach statement support. #8017

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Add forloop statement support, due to lack of dyn array support, currently static-length array is supported.

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Maybe you can refer to the implementation of Handle repeat loops. We can pass the cond to the BB1 when we enter. I guess this method can reduce accessing memory(like read and blokcing_assign ops) frequently 🤔. WDYT @fabianschuiki?

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Please add a few annotations. It's important for others. And thanks for your work on this 😄.

@@ -7,6 +7,7 @@
//===----------------------------------------------------------------------===//

#include "ImportVerilogInternals.h"
#include "mlir/IR/Diagnostics.h"
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nit: Don't include extra unnecessary headers.

Comment on lines +549 to +550
// CHECK: moore.blocking_assign %[[I]], %[[ADD2]] : i32
// CHECK: cf.br ^[[BB1]]
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Referring to repeat loops, we can avoid creating blocking_assign.

@hailongSun2000 hailongSun2000 changed the title [ImportVerilog] add forloop statement support [ImportVerilog] Add foreach statement support. Dec 27, 2024
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