[ImportVerilog] Add case inside #7928
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| always_comb begin | ||
| case (caseExpr) | ||
| 32'h1, 32'h2, 32'h3: result = 1; | ||
| default: result = 0; | ||
| endcase | ||
| end |
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Your example is not a case inside statement. Maybe the example in the SystemVerilog IEEE Std § 12.5.4 is better. What do @ankolesn think 😃?
logic [2:0] status;
always @(posedge clock)
priority case (status) inside
1, 3 : task1; // matches 'b001 and 'b011
3'b0?0, [4:7]: task2; // matches 'b000 'b010 'b0x0 'b0z0 'b100 'b101 'b110 'b111
endcase // priority case fails all other values including 'b00x 'b01x 'bxxx
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Thanks for your comments! I tried to fix it, you can check it 😃
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| module priority_case_test; | ||
| // CHECK: logic clock | ||
| logic clock; | ||
| // CHECK: logic [2:0] status | ||
| logic [2:0] status; | ||
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| task task1; | ||
| // CHECK: task1 executed | ||
| $display("task1 executed at time %0t", $time); | ||
| endtask | ||
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| task task2; | ||
| // CHECK: task2 executed | ||
| $display("task2 executed at time %0t", $time); | ||
| endtask | ||
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| initial begin | ||
| // CHECK: clock initialized to 0 | ||
| clock = 0; | ||
| // CHECK: clock toggles every 5 ns | ||
| forever #5 clock = ~clock; | ||
| end | ||
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| initial begin | ||
| // CHECK: Test Case 1: status = 3'b001 | ||
| status = 3'b001; | ||
| @(posedge clock); | ||
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| // CHECK: Test Case 2: status = 3'b011 | ||
| status = 3'b011; | ||
| @(posedge clock); | ||
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| // CHECK: Test Case 3: status = 3'b010 (matches task2) | ||
| status = 3'b010; | ||
| @(posedge clock); | ||
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| // CHECK: Test Case 4: status = 3'b100 (matches task2) | ||
| status = 3'b100; | ||
| @(posedge clock); | ||
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| // CHECK: Test Case 5: status = 3'b00x (no match) | ||
| status = 3'b00x; | ||
| @(posedge clock); | ||
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| // CHECK: Test Case 6: status = 3'b111 (matches task2) | ||
| status = 3'b111; | ||
| @(posedge clock); | ||
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| // CHECK: Test Case 7: status = 3'bxxx (no match) | ||
| status = 3'bxxx; | ||
| @(posedge clock); | ||
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| // CHECK: End simulation | ||
| $finish; | ||
| end | ||
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| always @(posedge clock) begin | ||
| // CHECK: Entering priority case | ||
| priority case (status) | ||
| // CHECK: Matches 3'b001 or 3'b011, executes task1 | ||
| 3'b001, 3'b011: task1; | ||
| // CHECK: Matches 3'b0?0 or [3'b100:3'b111], executes task2 | ||
| 3'b0?0, [3'b100:3'b111]: task2; | ||
| // CHECK: No match, default case | ||
| default: $display("No match for status = %b at time %0t", status, $time); | ||
| endcase | ||
| end |
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Hey @ankolesn, thanks a lot for working on this! One comment regarding your unit test: we don't simulate the design as part of the unit test, so things like $display(...) will not show up as prints in the output. Instead, the unit tests check that the expected IR operations get generated. For your PR, I'd add different examples that exercise interesting corner cases of your implementation. If you look through basic.sv, you should find existing tests for case statements that can give you some inspiration on how to do that. Then you can check if your code generates the correct IR ops for inside case statements.
| case CaseStatementCondition::Inside: | ||
| mlir::emitError(loc, "unsupported set membership case statement"); | ||
| return failure(); | ||
| std::vector<Value> values; |
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SmallVector per MLIR coding guidelines.
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| if (values.size() == 1) { | ||
| cond = builder.create<moore::WildcardEqOp>(loc, caseExpr, | ||
| values.front()); |
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nit: why use front here and [0] two lines later?
| return failure(); | ||
| } | ||
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| if (values.size() == 1) { |
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This conditional could be completely eliminated.
Implementation of functionality for checking whether a value belongs to a set of expressions (like inside in SystemVerilog)